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| Freescale Semiconductor Technical Data MPC852TEC Rev. 3.1, 01/2005 MPC852T Hardware Specifications This document contains detailed information for the MPC852T about power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics of the MPC852T. For information about functional characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual (MPC866UM). The MPC852T contains a PowerPCTM processor core. 1 Overview The MPC852T PowerQUICCTM is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points. The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU on the MPC852T is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Calculation and Measurement . . . . . . . . . . . 8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Supply and Power Sequencing . . . . . . . . . . . 10 Mandatory Reset Configurations . . . . . . . . . . . . . . . 11 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 56 Mechanical Data and Ordering Information . . . . . . . 60 Document Revision History . . . . . . . . . . . . . . . . . . . 78 (c) Freescale Semiconductor, Inc., 2004. All rights reserved. Features 2 Features The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). Figure 1 shows the MPC852T block diagram. The following list summarizes the key MPC852T features: * * Embedded MPC8xx core up to 100 MHz Maximum frequency operation of the external bus is 66 MHz -- The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes. -- The 80 MHz / 100 MHz core frequencies support 2:1 mode only. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit general-purpose registers (GPRs) -- The core performs branch prediction with conditional prefetch, without conditional execution. -- 4-Kbyte data cache and 4-Kbyte instruction cache - 4-Kbyte instruction cache is two-way, set-associative with 128 sets. - 4-Kbyte data cacheis two-way, set-associative with 128 sets. - Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. - Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. -- MMUs with 32-entry TLB, fully associative instruction, and data TLBs -- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces, and 16 protection groups Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank -- Up to 30 wait states programmable per memory bank -- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices -- DRAM controller-programmable to support most size and speed memory interfaces -- Four CAS lines, four WE lines, and one OE line -- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) -- Variable block sizes (32 Kbytes-256 Mbytes) -- Selectable write protection -- On-chip bus arbitration logic Fast Ethernet Controller (FEC) General-purpose timers -- Two 16-bit timers or one 32-bit timer -- Gate mode can enable or disable counting. -- Interrupt can be masked on reference match and event capture. MPC852T Hardware Specifications, Rev. 3.1 2 Freescale Semiconductor * * * * * * Features * * * System integration unit (SIU) -- Bus monitor -- Software watchdog -- Periodic interrupt timer (PIT) -- Clock synthesizer -- Decrementer and time base -- Reset controller -- IEEE 1149.1 test access port (JTAG) Interrupts -- Seven external interrupt request (IRQ) lines -- Seven port pins with interrupt capability -- Eighteen internal interrupt sources -- Programmable priority between SCCs -- Programmable highest-priority request Communications processor module (CPM) -- RISC controller -- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) * * * * * -- Supports continuous mode transmission and reception on all serial channels -- 8-Kbytes of dual-port RAM -- 8 serial DMA (SDMA) channels -- Three parallel I/O registers with open-drain capability Two baud rate generators -- Independent (can be connected toany SCC3/4 or SMC1) -- Allows changes during operation -- Autobaud support option Two SCCs (serial communication controllers) -- Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation -- HDLC/SDLC -- HDLC bus (implements an HDLC-based local area network (LAN)) -- Universal asynchronous receiver transmitter (UART) -- Totally transparent (bit streams) -- Totally transparent (frame-based with optional cyclic redundancy check (CRC)) One SMC (serial management channels) -- UART One SPI (serial peripheral interface) -- Supports master and slave modes -- Supports multimaster operation on the same bus PCMCIA interface -- Master (socket) interface, release 2.1 compliant MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 3 Features * * * -- Supports one independent PCMCIA socket; 8-memory or I/O windows supported Debug interface -- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data -- Supports conditions: = < > -- Each watchpoint can generate a break point internally. Normal high and normal low power modes to conserve power 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V Tolerant pins. 4-Kbyte Instruction Instruction Cache Bus System Interface Unit (SIU) Unified Bus Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Embedded MPC8xx Processor Core Instruction MMU 32-Entry ITLB Load/Store Bus 4-Kbyte Data Cache Data MMU 32-Entry DTLB Fast Ethernet Controller DMAs FIFOs 10/100 Base-T Media Access Control Parallel I/O 2 Baud Rate Generators 2 Interrupt 8-Kbyte Timers Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Timers 1 Virtual IDMA & 8 Serial DMA Channels MII SCC3 SCC4 SMC1 SPI Serial Interface (NMSI) Figure 1. MPC852T Block Diagram MPC852T Hardware Specifications, Rev. 3.1 4 Freescale Semiconductor Maximum Tolerated Ratings 3 Maximum Tolerated Ratings Table 1. Maximum Tolerated Ratings Rating Supply voltage 1 Symbol VDDL (core voltage) VDDH (I/O voltage) VDDSYN Difference between VDDL to VDDSYN Input voltage 2 Storage temperature range 1 2 This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1 provides the maximum ratings and operating temperatures. Value - 0.3 to 3.4 - 0.3 to 4 - 0.3 to 3.4 100 Unit V V V mV Vin Tstg GND - 0.3 to VDDH - 55 to +150 V C The power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Table 2. Operating Temperatures Rating Temperature 1 (standard) Symbol TA(min) Tj(max) Temperature (extended) TA(min) Tj(max) 1 Value 0 95 - 40 100 Unit C C C C Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as junction temperature, Tj. This device contains circuitry protecting against damage that high-static voltage or electrical fields cause; however, Motorola recommends taking normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). -- VDDH. 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC852T. MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 5 Power Dissipation Table 3. MPC852T Thermal Resistance Data Rating Junction to ambient 1 Environment Natural convection Single layer board (1s) Four layer board (2s2p) Air flow (200 ft/min) Single layer board (1s) Four layer board (2s2p) Junction to board 4 Junction to case 5 Junction to package top 6 Natural convection Air flow (200 ft/min) 1 Symbol RJA 2 RJMA 3 RJMA3 RJMA3 RJB RJC JT JT Value 49 32 41 29 24 13 3 2 Unit C/W 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal Per JEDEC JESD51-6 with the board horizontal Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 5 Power Dissipation Table 4. Power Dissipation (PD) Die Revision Bus Mode Frequency (MHz) 50 1:1 0 2:1 1 Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed. Typical 1 Maximum 2 110 150 140 170 210 140 180 160 200 250 Unit mW mW mW mW mW 66 66 80 100 Typical power dissipation is measured at 1.9 V. MPC852T Hardware Specifications, Rev. 3.1 6 Freescale Semiconductor DC Characteristics 2 Maximum power dissipation at VDDL and VDDSYN is at 1.9 V. and VDDH is at 3.465 V. NOTE Values in Table 4 represent VDDL-based power dissipation, and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application that buffer current can cause, depending on external circuitry. The VDDSYN power dissipation is negligible. 6 DC Characteristics Table 5. DC Electrical Specifications Characteristic Operating voltage VDDH VDDL VDDSYN Difference between VDDL to VDDSYN Input high voltage (all inputs except PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO) 1 Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins 1 Input leakage current, Vin = VDDH (Except TMS, TRST, DSCK, and DSDI) Input leakage current, Vin = 0 V (Except TMS, TRST, DSCK and DSDI pins) Input capacitance 2 VIH Symbol Min 3.135 1.7 1.7 -- 2.0 Max 3.465 1.9 1.9 100 3.465 Unit V V V mV V Table 5 provides the DC electrical characteristics for the MPC852T. VIL VIHC Iin GND 0.7 x VDDH -- 0.8 VDDH 100 V V A IIn IIn Cin -- -- -- 10 10 20 A A pF MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 7 Thermal Calculation and Measurement Table 5. DC Electrical Specifications (continued) Characteristic Output high voltage, IOH = -2.0 mA, VDDH = 3.0 V Except XTAL and open drain pins Output low voltage IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA 3 IOL = 5.3 mA 4 IOL = 7.0 mA (Txd1/pa14, txd2/pa12) IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET) 1 Symbol VOH Min 2.4 Max -- Unit V VOL -- 0.5 V The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant pins. 2 Input capacitance is periodically sampled. 3 A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CLK5/PA3, BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24, BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12, MII-TXERR/RXD3/PD11, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4, MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL 4 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30) 7 Thermal Calculation and Measurement NOTE The VDDSYN power dissipation is negligible. For the following discussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: TJ = TA +(RJA x PD) where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance (C/W) PD = power dissipation in package MPC852T Hardware Specifications, Rev. 3.1 8 Freescale Semiconductor Thermal Calculation and Measurement The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ-TA) are possible. 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. Thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB +(RJB x PD) where: RJB = junction-to-board thermal resistance (C/W) TB = board temperature C PD = power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 9 References 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT +(JT x PD) where: JT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors that cooling effects of the thermocouple wire cause. 8 References Semiconductor Equipment and Materials International(415) 964-5111 805 East Middlefield Rd Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or (Available from Global Engineering documents)303-397-7956 JEDEC Specifications http://www.jedec.org 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 9 Power Supply and Power Sequencing This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC852T is supplied with 3.3 V across VDDH and VSS (GND). The signal PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5 V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation. MPC852T Hardware Specifications, Rev. 3.1 10 Freescale Semiconductor Mandatory Reset Configurations One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply: * * VDDL must not exceed VDDH during power-on reset or power down. VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465. These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 2 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power-on reset, and the 1N5820 diodes regulate the maximum potential difference on power-down. VDDH MUR420 VDDL 1N5820 Figure 2. Example Voltage Sequencing Circuit 10 Mandatory Reset Configurations The MPC852T requires a mandatory configuration during reset. If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET assertion, the HRCW[DBGC] value that is needed to be set to binary X1 in the hardware reset configuration word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset. MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 11 Layout Practices The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the mandatory value in Table 6 in the boot code after the reset deasserts. Table 6. Mandatory Reset Configuration of MPC852T Register/Configuration HRCW (Hardware reset configuration word) SIUMCR (SIU module configuration register) MBMR (Machine B mode register) PAPAR (Port A pin assignment register) PADIR (Port A Data Direction Register) PBPAR (Port B Pin Assignment Register) HRCW[DBGC] Field Value (binary) X1 SIUMCR[DBGC] X1 MBMR[GPLB4DIS} 0 PAPAR[4-7] PAPAR[12-15] PADIR[4-7] PADIR[12-15] PBPAR[14] PBPAR[16-23] PBPAR[26-27] PBDIR[14] PBDIR[16-23] PBDIR[26-27] PCPAR[8-11] PCDIR[14] PCDIR[8-11] PCDIR[14] 0 1 0 PBDIR (Port B Data Direction Register) 1 PCPAR (Port C Pin Assignment Register) PCDIR (Port C Data Direction Register) 0 1 11 Layout Practices Each VDD pin on the MPC852T should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as VDD and GND planes should be used. All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized to minimize undershoot and reflections that these fast output switching times cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads, because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL MPC852T Hardware Specifications, Rev. 3.1 12 Freescale Semiconductor Bus Signal Timing supply pins. For more information, please refer to MPC866 User's Manual, Section 14.4.3, "Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)." 12 Bus Signal Timing The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for standard part frequencies. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Freq 50MHz Min Core Freq Bus Freq 40 40 Max 50 50 66MHz Min 40 40 Max 66.67 66.67 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part Freq 50MHz Min Core Freq Bus Freq 2:1 40 20 Max 50 25 66MHz Min 40 20 Max 66.67 33.33 80MHz Min 40 20 Max 80 40 100MHz Min 40 20 Max 100 50 Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz. The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay Table 9. Bus Operation Timings 33 MHz Num Characteristic Min B1 B1a Bus period (CLKOUT) See Table 7 EXTCLK to CLKOUT phase skew - If CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. CLKOUT frequency jitter peak-to-peak Frequency jitter on EXTCLK 1 -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 ns ns 40 MHz 50 MHz 66 MHz Unit B1b B1c -- -- 1 0.50 -- -- 1 0.50 -- -- 1 0.50 -- -- 1 0.50 ns % MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 13 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B1d CLKOUT phase jitter peak-to-peak for OSCLK 15 MHz CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz B2 B3 B4 B5 B7 CLKOUT pulse width low (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT pulse width high (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT rise time CLKOUT fall time CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 x B1) CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR output hold (MIN = 0.25 x B1) CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3) valid (MAX = 0.25 x B1 + 6.3) CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR valid (MAX = 0.25 x B1 + 6.3) CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS Valid 3 (MAX = 0.25 x B1 + 6.3) CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3) CLKOUT to TS, BB assertion (MAX = 0.25 x B1 + 6.0) -- Max 4 Min -- Max 4 Min -- Max 4 Min -- Max 4 ns 40 MHz 50 MHz 66 MHz Unit -- 5 -- 5 -- 5 -- 5 ns 12.1 12.1 -- -- 7.60 18.2 18.2 4.00 4.00 -- 10.0 10.0 -- -- 6.30 15.0 15.0 4.00 4.00 -- 8.0 8.0 -- -- 5.00 12.0 12.0 4.00 4.00 -- 6.1 6.1 -- -- 3.80 9.1 9.1 4.00 4.00 -- ns ns ns ns ns B7a B7b 7.60 7.60 -- -- 6.30 6.30 -- -- 5.00 5.00 -- -- 3.80 3.80 -- -- ns ns B8 -- 13.80 -- 12.50 -- 11.30 -- 10.00 ns B8a B8b -- -- 13.80 13.80 -- -- 12.50 12.50 -- -- 11.30 11.30 -- -- 10.00 10.00 ns ns B9 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B11 7.60 2.50 13.60 9.30 6.30 2.50 12.30 9.30 5.00 2.50 11.00 9.30 3.80 2.50 9.80 9.80 ns ns B11a CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.30 2) B12 CLKOUT to TS, BB negation (MAX = 0.25 x B1 + 4.8) 7.60 2.50 12.30 9.00 6.30 2.50 11.00 9.00 5.00 2.50 9.80 9.00 3.80 2.50 8.50 9.00 ns ns B12a CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.00) B13 CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns MPC852T Hardware Specifications, Rev. 3.1 14 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B13a CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5) B14 B15 B16 CLKOUT to TEA assertion (MAX = 0.00 x B1 + 9.00) CLKOUT to TEA High-Z (MIN = 0.00 x B1 + 2.50) TA, BI valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 6.00) 2.50 Max 15.00 Min 2.50 Max 15.00 Min 2.50 Max 15.00 Min 2.50 Max 15.00 ns 40 MHz 50 MHz 66 MHz Unit 2.50 2.50 6.00 4.50 4.00 1.00 2.00 6.00 1.00 4.00 2.00 7.60 -- 7.60 9.00 15.00 -- -- -- -- -- -- -- -- -- 13.80 8.00 13.80 2.50 2.50 6.00 4.50 4.00 1.00 2.00 6.00 1.00 4.00 2.00 6.30 -- 6.30 9.00 15.00 -- -- -- -- -- -- -- -- -- 12.50 8.00 12.50 2.50 2.50 6.00 4.50 4.00 1.00 2.00 6.00 1.00 4.00 2.00 5.00 -- 5.00 9.00 15.00 -- -- -- -- -- -- -- -- -- 11.30 8.00 11.30 2.50 2.50 6.00 4.50 4.00 2.00 2.00 6.00 2.00 4.00 2.00 3.80 -- 3.80 9.00 15.00 -- -- -- -- -- -- -- -- -- 10.00 8.00 10.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 4.5) B16b BB, BG, BR, valid to CLKOUT (setup time) 3 (4MIN = 0.00 x B1 +.000) B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0.00 x B1 + 1.00 4) B17a CLKOUT to KR, RETRY, CR valid (hold time) (MIN = 0.00 x B1 + 2.00) B18 B19 B20 B21 B22 D(0:31), DP(0:3) valid to CLKOUT rising edge (setup time) 5 (MIN = 0.00 x B1 + 6.00) CLKOUT rising edge to D(0:31), DP(0:3) valid (hold time) 5 (MIN = 0.00 x B1 + 1.00 6) D(0:31), DP(0:3) valid to CLKOUT falling edge (setup time) 7(MIN = 0.00 x B1 + 4.00) CLKOUT falling edge to D(0:31), DP(0:3) valid (hold Time) 7 (MIN = 0.00 x B1 + 2.00) CLKOUT rising edge to CS asserted GPCM ACS = 00 (MAX = 0.25 x B1 + 6.3) B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00) B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3) B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6) B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 + 8.00) 10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 15 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B24 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00) 5.60 Max -- Min 4.30 Max -- Min 3.00 Max -- Min 1.80 Max -- ns 40 MHz 50 MHz 66 MHz Unit B24a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 2.00) B25 CLKOUT rising edge to OE, WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1 + 9.00) CLKOUT rising edge to OE negated (MAX = 0.00 x B1 + 9.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns -- 9.00 9.00 9.00 9.00 ns B26 B27 2.00 35.90 9.00 -- 2.00 29.30 9.00 -- 2.00 23.00 9.00 -- 2.00 16.90 9.00 -- ns ns B27a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 2.00) B28 CLKOUT rising edge to WE(0:3)/BS_B[0:3] negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00) 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns -- 9.00 -- 9.00 -- 9.00 -- 9.00 ns B28a CLKOUT falling edge to WE(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1 ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B28c CLKOUT falling edge to WE(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0,1 CSNT = 1 write access TRLX = 0,1 CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6) B28d CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6) B29 WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns -- 14.30 -- 13.00 -- 11.80 -- 10.50 ns 10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns -- 18.00 -- 18.00 -- 14.30 -- 12.30 ns 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B29a WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns MPC852T Hardware Specifications, Rev. 3.1 16 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B29b CS negated to D(0:31), DP(0:3), High Z GPCM write access, ACS = 00, TRLX = 0,1 & CSNT = 0 (MIN = 0.25 x B1 - 2.00) 5.60 Max -- Min 4.30 Max -- Min 3.00 Max -- Min 1.80 Max -- ns 40 MHz 50 MHz 66 MHz Unit B29c CS negated to D(0:31), DP(0:3) High-Z GPCM 13.20 write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50 x B1 - 2.00) B29d WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00) 43.50 -- 10.50 -- 8.00 -- 5.60 -- ns -- 35.50 -- 28.00 -- 20.70 -- ns B29e CS negated to D(0:31), DP(0:3) High-Z GPCM 43.50 write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) B29f WE(0:3/BS_B[0:3]) negated to D(0:31), DP(0:3) High Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 6.30) B29g CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30) 5.00 -- 35.50 -- 28.00 -- 20.70 -- ns -- 3.00 -- 1.10 -- 0.00 -- ns 5.00 -- 3.00 -- 1.10 -- 0.00 -- ns B29h WE(0:3)/BS_B[0:3] negated to D(0:31), 38.40 DP(0:3) High Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 3.30) B29i CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 3.30) B30 CS, WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) Invalid GPCM write access 8 (MIN = 0.25 x B1 - 2.00) 38.40 -- 31.10 -- 24.20 -- 17.50 -- ns -- 31.10 -- 24.20 -- 17.50 -- ns 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B30a WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) Invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 - 2.00) B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 17 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B30c WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 - 3.00) B30d WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 B31 CLKOUT falling edge to CS valid - as requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 X B1 + 6.00) 8.40 Max -- Min 6.40 Max -- Min 4.50 Max -- Min 2.70 Max -- ns 40 MHz 50 MHz 66 MHz Unit 38.67 -- 31.38 -- 24.50 -- 17.83 -- ns 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B31a CLKOUT falling edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) B31b CLKOUT rising edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) B31c CLKOUT rising edge to CS valid- as requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B31d CLKOUT falling edge to CS valid, as requested 13.30 by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6) B32 CLKOUT falling edge to BS valid- as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80) B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) B32c CLKOUT rising edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns MPC852T Hardware Specifications, Rev. 3.1 18 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B32d CLKOUT falling edge to BS valid- as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60) B33 CLKOUT falling edge to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 13.30 Max 18.00 Min 11.30 Max 16.00 Min 9.40 Max 14.10 Min 7.60 Max 12.30 ns 40 MHz 50 MHz 66 MHz Unit 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B33a CLKOUT rising edge to GPL Valid - as requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) B34 A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B34a A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) B34b A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by CST2 in the corresponding word in UPM (MIN = 0.75 x B1 2.00) B35 A(0:31), BADDR(28:30) to CS valid - as requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns 20.70 -- 16.70 -- 13.00 -- 9.40 -- ns 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid - As Requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 - 2.00) B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) UPWAIT valid to CLKOUT falling edge 9 (MIN = 0.00 x B1 + 6.00) CLKOUT falling edge to UPWAIT valid 9 (MIN = 0.00 x B1 + 1.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns 20.70 -- 16.70 -- 13.00 -- 9.40 -- ns 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B37 B38 6.00 1.00 -- -- 6.00 1.00 -- -- 6.00 1.00 -- -- 6.00 1.00 -- -- ns ns MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 19 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B39 B40 B41 B42 B43 1 40 MHz Min 7.00 7.00 7.00 2.00 -- Max -- -- -- -- TBD 50 MHz Min 7.00 7.00 7.00 2.00 -- Max -- -- -- -- TBD 66 MHz Unit Min 7.00 7.00 7.00 2.00 -- Max -- -- -- -- TBD ns ns ns ns ns Max -- -- -- -- TBD AS valid to CLKOUT rising edge 10 (MIN = 0.00 x B1 + 7.00) A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 x B1 + 7.00) CLKOUT rising edge to TS valid (hold time) (MIN = 0.00 x B1 + 2.00) AS negation to memory controller signals negation (MAX = TBD) 7.00 7.00 7.00 2.00 -- If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum allowed jitter on EXTAL can be up to 2%. 2 For part speeds above 50MHz, use 9.80ns for B11a. 3 The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for BG input is relevant when the MPC852T is selected to work with external bus arbiter. 4 For part speeds above 50MHz, use 2ns for B17. 5 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 6 For part speeds above 50MHz, use 2ns for B19. 7 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 8 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. 9 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18. 10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 21. MPC852T Hardware Specifications, Rev. 3.1 20 Freescale Semiconductor Bus Signal Timing Figure 3 is the control timing diagram. 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 2.0 V CLKOUT A B C D Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 3. Control Timing Figure 4 provides the timing for the external clock. CLKOUT B1 B1 B4 B5 B3 B2 Figure 4. External Clock Timing MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 21 Bus Signal Timing Figure 5 provides the timing for the synchronous output signals. CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 5. Synchronous Output Signals Timing Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 TS, BB B13a B11a B12a B12 TA, BI B14 B15 TEA Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC852T Hardware Specifications, Rev. 3.1 22 Freescale Semiconductor Bus Signal Timing Figure 7 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 7. Synchronous Input Signals Timing Figure 8 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 8. Input Data Timing in Normal Case MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 23 Bus Signal Timing Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure 9. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 10 through Figure 13 provide the timing for the external bus read that various GPCM factors control. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31], DP[0:3] B19 B26 B23 B12 Figure 10. External Bus Read Timing (GPCM Controlled--ACS = 00) MPC852T Hardware Specifications, Rev. 3.1 24 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B24 OE B18 D[0:31], DP[0:3] B19 B25 B26 Figure 11. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] B22c B22b B12 B23 CSx B24a B25 B26 OE B18 D[0:31], DP[0:3] B19 Figure 12. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 11) MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 25 Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B27 OE B27a B22b B22c B26 B18 B19 D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled--TRLX = 0 or 1, ACS = 10, ACS = 11) MPC852T Hardware Specifications, Rev. 3.1 26 Freescale Semiconductor Bus Signal Timing Figure 14 through Figure 16 provide the timing for the external bus write that various GPCM factors control. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B9 B29b B12 B30 B23 B28 B29 Figure 14. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 0) MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 27 Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29a B29f B29c B29g B28b B28d B30a B30c B12 B23 B9 Figure 15. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 1) MPC852T Hardware Specifications, Rev. 3.1 28 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29d B29h B29e B29i B28b B28d B30b B30d B12 B23 B29b B9 Figure 16. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 1) MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 29 Bus Signal Timing Figure 17 provides the timing for the external bus that the UPM controls. CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3] B35 B36 B35a B35b B33a B33 GPL_A[0:5], GPL_B[0:5] Figure 17. External Bus Timing (UPM Controlled Signals) MPC852T Hardware Specifications, Rev. 3.1 30 Freescale Semiconductor Bus Signal Timing Figure 18 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 31 Bus Signal Timing Figure 20 provides the timing for the synchronous external master access that the GPCM controls. CLKOUT B41 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx B42 Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 21 provides the timing for the asynchronous external master memory access that the GPCM controls. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled--ACS = 00) Figure 22 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 22. Asynchronous External Master--Control Signals Negation Timing MPC852T Hardware Specifications, Rev. 3.1 32 Freescale Semiconductor Bus Signal Timing Table 10 provides interrupt timing for the MPC852T. . Table 10. Interrupt Timing All Frequencies Num Characteristic 1 Min I39 I40 I41 I42 I43 1 Unit Max ns ns ns ns -- IRQx valid to CLKOUT rising edge (set up time) IRQx hold time after CLKOUT IRQx pulse width low IRQx pulse width high IRQx edge-to-edge time 6.00 2.00 3.00 3.00 4xTCLOCKOUT The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level-sensitive. The IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and have no direct relation with the total system interrupt latency that the MPC852T is able to support. Figure 23 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 23. Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 IRQx I43 I43 I42 Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 33 Bus Signal Timing Table 11 shows the PCMCIA timing for the MPC852T. Table 11. PCMCIA Timing 33 MHz Num Characteristic Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 1 40 MHz Min 16.70 23.00 6.30 7.30 6.30 6.30 -- 2.00 6.30 -- 4.30 8.00 2.00 Max -- -- 14.30 -- 14.30 14.30 11.00 11.00 12.50 14.30 -- -- -- 50 MHz Min 13.00 18.00 5.00 6.00 5.00 5.00 -- 2.00 5.00 -- 3.00 8.00 2.00 Max -- -- 13.00 -- 13.00 13.00 11.00 11.00 11.30 13.00 -- -- -- 66 MHz Unit Min 9.40 13.20 3.80 4.80 3.80 3.80 -- 2.00 3.80 -- 1.80 8.00 2.00 Max -- -- 11.80 -- 11.80 11.80 11.00 11.00 10.00 11.80 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Max -- -- 15.60 -- 15.60 15.60 11.00 11.00 13.80 15.60 -- -- -- A(0:31), REG valid to PCMCIA Strobe asserted. 1 (MIN = 0.75 x B1 - 2.00) A(0:31), REG valid to ALE negation.1 (MIN = 1.00 x B1 - 2.00) CLKOUT to REG valid (MAX = 0.25 x B1 + 8.00) CLKOUT to REG Invalid. (MIN = 0.25 x B1 + 1.00) CLKOUT to CE1, CE2 asserted. (MAX = 0.25 x B1 + 8.00) CLKOUT to CE1, CE2 negated. (MAX = 0.25 x B1 + 8.00) CLKOUT to PCOE, IORD, PCWE, IOWR assert time. (MAX = 0.00 x B1 + 11.00) CLKOUT to PCOE, IORD, PCWE, IOWR negate time. (MAX = 0.00 x B1 + 11.00) CLKOUT to ALE assert time (MAX = 0.25 x B1 + 6.30) CLKOUT to ALE negate time (MAX = 0.25 x B1 + 8.00) PCWE, IOWR negated to D(0:31) invalid.1 (MIN = 0.25 x B1 - 2.00) WAITA and WAITB valid to CLKOUT rising edge.1 (MIN = 0.00 x B1 + 8.00) CLKOUT rising edge to WAITA and WAITB invalid.1 (MIN = 0.00 x B1 + 2.00) 20.70 28.30 7.60 8.60 7.60 7.60 -- 2.00 7.60 -- 5.60 8.00 2.00 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITA assertion is effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC852T PowerQUICC User s Manual. MPC852T Hardware Specifications, Rev. 3.1 34 Freescale Semiconductor Bus Signal Timing Figure 25 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 Figure 25. PCMCIA Access Cycles Timing External Bus Read MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 35 Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCWE, IOWR P52 ALE B8 D[0:31] B9 P53 P52 P51 P54 P49 P45 P47 Figure 26. PCMCIA Access Cycles Timing External Bus Write Figure 27 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITA Figure 27. PCMCIA WAIT Signals Detection Timing MPC852T Hardware Specifications, Rev. 3.1 36 Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC852T. Table 12. PCMCIA Port Timing 33 MHz Num Characteristic Min J95 J96 J97 J98 1 40 MHz Min -- 21.70 5.00 1.00 Max 19.00 -- -- -- 50 MHz Min -- 18.00 5.00 1.00 Max 19.00 -- -- -- 66 MHz Unit Min -- 14.40 5.00 1.00 Max 19.00 -- -- -- ns ns ns ns Max 19.00 -- -- -- CLKOUT to OPx Valid (MAX = 0.00 x B1 + 19.00) HRESET negated to OPx drive 1(MIN = 0.75 x B1 + 3.00) IP_Xx valid to CLKOUT rising edge (MIN = 0.00 x B1 + 5.00) CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 x B1 + 1.00) -- 25.70 5.00 1.00 OP2 and OP3 only. Figure 28 provides the PCMCIA output port timing for the MPC852T. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 28. PCMCIA Output Port Timing Figure 29 provides the PCMCIA output port timing for the MPC852T. CLKOUT P59 P60 Input Signals Figure 29. PCMCIA Input Port Timing MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 37 Bus Signal Timing Table 13 shows the debug port timing for the MPC852T. Table 13. Debug Port Timing All Frequencies Num Characteristic Min J82 J83 J84 J85 J86 J87 J88 DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 3xTCLOCKOUT 1.25xTCLOCKOUT 0.00 8.00 5.00 0.00 0.00 Max -- -- 3.00 -- -- 15.00 2.00 -- -- ns ns ns ns ns Unit Figure 30 provides the input timing for the debug port clock. DSCK D61 D61 D63 D62 D62 D63 Figure 30. Debug Port Clock Input Timing Figure 31 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 31. Debug Port Timings MPC852T Hardware Specifications, Rev. 3.1 38 Freescale Semiconductor Bus Signal Timing Table 14 shows the reset timing for the MPC852T. Table 14. Reset Timing 33 MHz Num Characteristic Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 CLKOUT to HRESET high impedance (MAX = 0.00 x B1 + 20.00) CLKOUT to SRESET high impedance (MAX = 0.00 x B1 + 20.00) RSTCONF pulse width (MIN = 17.00 x B1) -- Configuration data to HRESET rising edge set up time (MIN = 15.00 x B1 + 50.00) -- -- 515.20 -- 504.50 Max 20.00 20.00 -- -- -- -- -- -- 25.00 25.00 25.00 Min -- -- 425.00 -- 425.00 350.00 0.00 0.00 -- -- -- Max 20.00 20.00 -- -- -- -- -- -- 25.00 25.00 25.00 Min -- -- 340.00 -- 350.00 350.00 0.00 0.00 -- -- -- Max 20.00 20.00 -- -- -- -- -- -- 25.00 25.00 25.00 Min -- -- 257.60 -- 277.30 350.00 0.00 0.00 -- -- -- Max 20.00 20.00 -- -- -- -- -- -- 25.00 25.00 25.00 ns ns ns -- ns ns ns ns ns ns ns 40 MHz 50 MHz 66 MHz Unit Configuration data to RSTCONF rising edge set 350.00 up time (MIN = 0.00 x B1 + 350.00) Configuration data hold time after RSTCONF negation (MIN = 0.00 x B1 + 0.00) Configuration data hold time after HRESET negation (MIN = 0.00 x B1 + 0.00) HRESET and RSTCONF asserted to data out drive (MAX = 0.00 x B1 + 25.00) RSTCONF negated to data out high impedance. (MAX = 0.00 x B1 + 25.00) CLKOUT of last rising edge before chip three-states HRESET to data out high impedance. (MAX = 0.00 x B1 + 25.00) DSDI, DSCK set up (MIN = 3.00 x B1) DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00) SRESET negated to CLKOUT rising edge for DSDI and DSCK sample (MIN = 8.00 x B1) 0.00 0.00 -- -- -- J92 J93 J94 J95 90.90 0.00 242.40 -- -- -- 75.00 0.00 200.00 -- -- -- 60.00 0.00 160.00 -- -- -- 45.50 0.00 121.20 -- -- -- ns ns ns MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 39 Bus Signal Timing Figure 32 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 Figure 32. Reset Timing--Configuration from Data Bus Figure 33 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 33. Reset Timing--Data Bus Weak Drive during Configuration MPC852T Hardware Specifications, Rev. 3.1 40 Freescale Semiconductor IEEE 1149.1 Electrical Specifications Figure 34 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 Figure 34. Reset Timing--Debug Port Configuration 13 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC852T shown in Figure 35 through Figure 38. Table 15. JTAG Timing All Frequencies Num Characteristic Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to output valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid 100.00 40.00 0.00 5.00 25.00 -- 0.00 -- 100.00 40.00 -- -- -- 50.00 50.00 Max -- -- 10.00 -- -- 27.00 -- 20.00 -- -- 50.00 50.00 50.00 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 41 IEEE 1149.1 Electrical Specifications TCK J82 J82 J84 J83 J83 J84 Figure 35. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 TDO J89 Figure 36. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 37. JTAG TRST Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 42 Freescale Semiconductor CPM Electrical Characteristics TCK J92 Output Signals J93 Output Signals J95 Output Signals J96 J94 Figure 38. Boundary Scan (JTAG) Timing Diagram 14 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC852T. 14.1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C interrupts. Table 16. Port C Interrupt Timing 33.34 MHz Num Characteristic Min 35 36 Port C interrupt pulse width low (edge-triggered mode) Port C interrupt minimum time between active edges 55 55 Max -- -- ns ns Unit Figure 39 shows the port C interrupt detection timing. 36 Port C (Input) 35 Figure 39. Port C Interrupt Detection Timing MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 43 CPM Electrical Characteristics 14.2 IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shown in Figure 40 through Figure 43. Table 17. IDMA Controller Timing All Frequencies Num Characteristic Min 40 41 42 43 44 45 46 1 Unit Max -- -- 12 12 20 15 -- ns ns ns ns ns ns ns DREQ setup time to clock high DREQ hold time from clock high 1 7 3 -- -- -- -- 7 SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time (applies to external TA) Applies to high-to-low mode (EDM=1) CLKO (Output) 41 40 DREQ (Input) Figure 40. IDMA External Requests Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 44 Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 46 TA (Input) 43 SDACK Figure 41. SDACK Timing Diagram--Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 DATA 44 TA (Output) SDACK Figure 42. SDACK Timing Diagram--Peripheral Write, Internally-Generated TA MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 45 CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 45 TA (Output) SDACK Figure 43. SDACK Timing Diagram--Peripheral Read, Internally-Generated TA 14.3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Figure 44. Table 18. Baud Rate Generator Timing All Frequencies Num Characteristic Min 50 51 52 BRGO rise and fall time BRGO duty cycle BRGO cycle -- 40 40 Max 10 60 -- ns % ns Unit 50 BRGOX 51 52 50 51 Figure 44. Baud Rate Generator Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 46 Freescale Semiconductor CPM Electrical Characteristics 14.4 Timer AC Electrical Specifications Table 19 provides the general-purpose timer timings as shown in Figure 45. Table 19. Timer Timing All Frequencies Num Characteristic Min 61 62 63 64 65 TIN/TGATE rise and fall time TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO low to TOUT valid 10 1 2 3 3 Max -- -- -- -- 25 ns clk clk clk ns Unit CLKO 60 61 TIN/TGATE (Input) 61 65 TOUT (Output) 64 63 62 Figure 45. CPM General-Purpose Timers Timing Diagram 14.5 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Table 20. NMSI External Clock Timing All Frequencies Num Characteristic Min 100 101 102 103 104 105 RCLK3 and TCLK3 width high 1 RCLK3 and TCLK3 width low RCLK3 and TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time to TCLK3 rising edge 1/SYNCCLK 1/SYNCCLK +5 -- 0.00 0.00 5.00 Max -- -- 15.00 50.00 50.00 -- ns ns ns ns ns ns Unit MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 47 CPM Electrical Characteristics Table 20. NMSI External Clock Timing (continued) All Frequencies Num Characteristic Min 106 107 108 1 2 Unit Max -- -- -- ns ns ns RXD3 setup time to RCLK3 rising edge RXD3 hold time from RCLK3 rising edge 2 CD3 setup Time to RCLK3 rising edge 5.00 5.00 5.00 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1. Also applies to CD and CTS hold time when they are used as an external sync signal. Table 21 provides the NMSI internal clock timing. Table 21. NMSI Internal Clock Timing All Frequencies Num Characteristic Min 100 102 103 104 105 106 107 108 1 2 Unit Max SYNCCLK/3 -- 30.00 30.00 -- -- -- -- MHz ns ns ns ns ns ns ns RCLK3 and TCLK3 frequency 1 RCLK3 and TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time to TCLK3 rising edge RXD3 setup time to RCLK3 rising edge RXD3 hold time from RCLK3 rising edge 2 CD3 setup time to RCLK3 rising edge 0.00 -- 0.00 0.00 40.00 40.00 0.00 40.00 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1. Also applies to CD and CTS hold time when they are used as an external sync signals. MPC852T Hardware Specifications, Rev. 3.1 48 Freescale Semiconductor CPM Electrical Characteristics Figure 46 through Figure 48 show the NMSI timings. RCLK3 102 106 RxD3 (Input) 107 108 CD3 (Input) 102 101 100 107 CD3 SYNC Input) Figure 46. SCC NMSI Receive Timing Diagram TCLK3 102 102 101 100 TxD3 (Output) 103 105 RTS3 (Output) 104 104 CTS3 (Input) 107 CTS3 (SYNC Input) Figure 47. SCC NMSI Transmit Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 49 CPM Electrical Characteristics TCLK3 102 102 101 100 TxD3 (Output) 103 RTS3 (Output) 104 105 CTS3 (Echo Input) 107 104 Figure 48. HDLC Bus Timing Diagram 14.6 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 49 through Figure 53. Table 22. Ethernet Timing All Frequencies Num Characteristic Min 120 121 122 123 124 125 126 127 128 129 130 131 132 133 CLSN width high RCLK3 rise/fall time RCLK3 width low RCLK3 clock period 1 RXD3 setup time RXD3 hold time RENA active delay (from RCLK3 rising edge of the last data bit) RENA width low TCLK3 rise/fall time TCLK3 width low TCLK3 clock period1 40 -- 40 80 20 5 10 100 -- 40 99 -- 6.5 10 Max -- 15 -- 120 -- -- -- -- 15 -- 101 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TXD3 active delay (from TCLK3 rising edge) TXD3 inactive delay (from TCLK3 rising edge) TENA active delay (from TCLK3 rising edge) MPC852T Hardware Specifications, Rev. 3.1 50 Freescale Semiconductor CPM Electrical Characteristics Table 22. Ethernet Timing (continued) All Frequencies Num Characteristic Min 134 135 136 137 138 139 1 2 Unit Max 50 50 50 -- 20 20 ns ns ns CLK ns ns TENA inactive delay (from TCLK3 rising edge) RSTRT active delay (from TCLK3 falling edge) RSTRT inactive delay (from TCLK3 falling edge) REJECT width low CLKO1 low to SDACK asserted 2 CLKO1 low to SDACK negated 2 10 10 10 1 -- -- The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure 49. Ethernet Collision Timing Diagram RCLK3 121 124 RxD3 (Input) 125 126 127 RENA(CD3) (Input) 121 123 Last Bit Figure 50. Ethernet Receive Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 51 CPM Electrical Characteristics TCLK3 128 131 TxD3 (Output) 132 133 TENA(RTS3) (Input) 134 128 121 129 RENA(CD3) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 51. Ethernet Transmit Timing Diagram RCLK3 RxD3 (Input) 0 1 Start Frame De- 1 BIT1 BIT2 136 125 RSTRT (Output) Figure 52. CAM Interface Receive Start Timing Diagram REJECT 137 Figure 53. CAM Interface REJECT Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 52 Freescale Semiconductor CPM Electrical Characteristics 14.7 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Figure 54 and Figure 55. Table 23. SPI Master Timing All Frequencies Num Characteristic Min 160 161 162 163 164 165 166 167 MASTER cycle time MASTER clock (SCK) high or low time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 15 0 -- 0 -- -- Max 1024 512 -- -- 10 -- 15 15 tcyc tcyc ns ns ns ns ns ns Unit SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb Data 165 167 SPIMOSI (Output) msb Data lsb 166 lsb 164 166 msb msb 167 167 160 166 Figure 54. SPI Master (CP = 0) Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 53 CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 55. SPI Master (CP = 1) Timing Diagram 14.8 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown in Figure 56 and Figure 57. Table 24. SPI Slave Timing All Frequencies Num Characteristic Min 170 171 172 173 174 175 176 177 Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time 2 15 15 1 1 20 20 -- Max -- -- -- -- -- -- -- 50 tcyc ns ns tcyc tcyc ns ns ns Unit MPC852T Hardware Specifications, Rev. 3.1 54 Freescale Semiconductor CPM Electrical Characteristics SPISEL (Input) 172 174 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) msb 175 176 SPIMOSI (Input) msb Data Data 179 181 182 lsb msb lsb 181 182 178 Undef msb 182 170 181 171 Figure 56. SPI Slave (CP = 0) Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 55 FEC Electrical Characteristics SPISEL (Input) 172 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) Undef 175 176 SPIMOSI (Input) msb msb Data 179 181 182 Data lsb msb lsb 182 178 msb 182 181 181 170 174 Figure 57. SPI Slave (CP = 1) Timing Diagram 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK) The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%. Table 25 provides information on the MII receive signal timing. Table 25. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns MII_RX_CLK period MII_RX_CLK period MPC852T Hardware Specifications, Rev. 3.1 56 Freescale Semiconductor FEC Electrical Characteristics Figure 58 shows MII receive signal timing. M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 58. MII Receive Signal Timing Diagram 15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%. Table 26 provides information about the MII transmit signal timing,. Table 26. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MII_TX_CLK pulse width high MII_TX_CLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns -- MII_TX_CLK period MII_TX_CLK period Figure 59 shows the MII transmit signal timing diagram. MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 57 FEC Electrical Characteristics M7 MII_TX_CLK (input) M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure 59. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 27 provides information about the MII async inputs signal timing. Table 27. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max -- Unit MII_TX_CLK period Figure 60 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 60. MII Async Inputs Timing Diagram 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 28. MII Serial Management Channel Timing Num M10 M11 M12 M13 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup MII_MDIO (input) to MII_MDC rising edge hold Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns MPC852T Hardware Specifications, Rev. 3.1 58 Freescale Semiconductor FEC Electrical Characteristics Table 28. MII Serial Management Channel Timing (continued) Num M14 M15 MII_MDC pulse width high MII_MDC pulse width low Characteristic Min 40% 40% Max 60% 60% Unit MII_MDC period MII_MDC period Figure 61 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure 61. MII Serial Management Channel Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 59 Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 29 identifies the packages and operating frequencies orderable for the MPC852T. Table 29. MPC852T Package/Frequency Orderable Package Type Plastic ball grid array (VR and ZT suffix) Temperature (Tj) 0C to 95C Frequency (MHz) 50 Order Number MPC852TVR50 MPC852TZT50 MPC852TVR66 MPC852TZT66 MPC852TVR80 MPC852TZT80 MPC852TVR100 MPC852TZT100 TBD 66 80 100 Plastic ball grid array (CVR suffix) - 40C to 100C 66 16.1 Pin Assignments The following sections give the pinout and pin listing for the JEDEC Compliant and the non-JEDEC versions of the 16 x 16 PBGA package. MPC852T Hardware Specifications, Rev. 3.1 60 Freescale Semiconductor Mechanical Data and Ordering Information 16.1.1 The JEDEC Compliant Pinout Figure 62 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User's Manual. NOTE: This is the top view of the device. A N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C B WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C C VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C PC15 D BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL E BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 F CR MII_COL BB TA PB30 TDO TMS TRST G VFLS_1 RSV BURST BG PB28 TDI VDDL MDIO H ALE_A DSCK VFLS_0 FRZ GND TCK PB25 PA10 PB24 J KR AS BADDR30 HRESET PC5 PC7 PA8 PA9 K OP0 OP1 OP2 RSTCONF VDDH PD13 PA2 PC6 PA3 L OP3BADDR29 BADDR28 VDDL N/C PC4 PA1 PB15 M EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14 D9 IRQ1 PD3 PD8 PD15 VDDL PA0 N XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 P PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 R VDDL IP_A7 N/C 1 IP_A0 2 IP_A2 IP_A4 3 DP3 DP2 4 D31 D30 5 D28 D7 6 D6 D22 7 D19 VDDL 8 D5 D18 9 D2 D3 10 D27 D1 11 D13 D4 12 D0 PD5 PD10 N/C T D8 MII_TXEN PD7 13 14 15 N/C 16 Figure 62. Pinout of the PBGA Package - JEDEC Standard MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 61 Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 30. Pin Assignments - JEDEC Standard Name A[0:31] Pin Number Type B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, Three-state (3.3V only) B11, A8, B10, B9, D8 E8 E7 B1 G3 D1 E2 F4 E3 D2 G2 J1 Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Output Bidirectional Active Pull-up (3.3V only) Bidirectional Active Pull-up (3.3V only) Open-drain Bidirectional Active Pull-up (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31] F1 Input (3.3V only) R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12, Bidirectional R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6, Three-state (3.3V only) P6, T5, R5 P4 P5 T4 R4 E1 Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6 BR MPC852T Hardware Specifications, Rev. 3.1 62 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments - JEDEC Standard (continued) Name BG BB FRZ IRQ6 IRQ0 IRQ1 M_TX_CLK IRQ7 CS[0:5] CS6 CS7 WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2-3] UPWAITA GPL_A4 GPL_A5 PORESET RSTCONF HRESET G4 F3 H4 P13 M11 N12 B2, A2, D3, C3, E6, C4 D4 A3 D6 Pin Number Type Bidirectional (3.3V only) Bidirectional Active Pull-up (3.3V only) Bidirectional (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Output Output Output Output C6 Output A5 Output B5 Output A6, D7, C7, B7 C5 D5 Output Output Output A4, B4 Output C2 E4 P1 K4 J4 Bidirectional (3.3V only) Output Input (3.3V only) Input (3.3V only) Open-drain MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 63 Mechanical Data and Ordering Information Table 30. Pin Assignments - JEDEC Standard (continued) Name SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG AS PA11 RXD3 M3 N1 M1 N6 N2 H1 E5 B3 N3 T2 M6 R3 M5 T3 N5 M7 R2 H2 H3, G1 K1 K2 K3 Pin Number Open-drain Analog Output Analog Input (1.8V only) Output Input (1.8V only) Output Output Output Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) Bidirectional (3.3V only) Output Bidirectional (3.3V only) Type L1 Bidirectional (3.3V only) L3, L2 J3 J2 E16 Output Output Input (3.3V only) Bidirectional (Optional: Open-drain) (5V tolerant) MPC852T Hardware Specifications, Rev. 3.1 64 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments - JEDEC Standard (continued) Name PA10 TXD3 PA9 RXD4 PA8 TXD4 PA3 CLK5 BRGO3 TIN3 PA2 CLK6 TOUT3 PA1 CLK7 BRGO4 TIN4 PA0 CLK8 TOUT4 PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB25 SMTXD1 PB24 SMRXD1 PB15 BRGO3 H15 J16 Pin Number Bidirectional (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Type J15 K16 K14 Bidirectional (5V tolerant) Bidirectional (5V tolerant) L15 M16 Bidirectional (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (5V tolerant) E13 F13 D15 G13 H14 H16 L16 MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 65 Mechanical Data and Ordering Information Table 30. Pin Assignments - JEDEC Standard (continued) Name PC15 DREQ0 PC13 RTS3 PC12 RTS4 PC7 CTS3 PC6 CD3 PC5 CTS4 SDACK1 PC4 CD4 PD15 MII_RXD3 PD14 MII_RXD2 PD13 MII_RXD1 PD12 MII_MDC PD11 RXD3 MII_TX_ER PD10 TXD3 MII_RXD0 PD9 RXD4 MII_TXD0 PD8 TXD4 MII_RX_CLK PD7 RTS3 MII_RX_ER C16 E14 E15 J14 K15 J13 Pin Number Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Type L14 M14 N16 K13 N15 P16 R15 N14 M13 T15 MPC852T Hardware Specifications, Rev. 3.1 66 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments - JEDEC Standard (continued) Name PD6 RTS4 MII_RX_DV PD5 MII_TXD3 PD4 MII_TXD2 PD3 MII_TXD1 TMS TDI DSDI TCK DSCK TRST TDO DSDO MII_CRS MII_MDIO MII_TXEN MII_COL VSSSYN VSSSYN1 VDDSYN GND VDDL VDDH N/C N13 Pin Number Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Input (5V tolerant) Input (5V tolerant) Input (5V tolerant) Input (5V tolerant) Output (5V tolerant) Input Bidirectional (5V tolerant) Output (5V tolerant) Input PLL analog GND PLL analog GND PLL analog VDD Type R14 P14 M12 F15 G14 H13 F16 F14 B6 G16 T14 F2 N4 P3 P2 G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, Power J10, J11, K6, K7, K8, K9, K10, K11 A7, C1, D16, G15, L4, M2, R1, M15, T8 F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 Power Power No-connect MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 67 Mechanical Data and Ordering Information 16.1.2 The non-JEDEC Pinout Figure 63 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User's Manual. NOTE: This figure shows the top view of the device. B N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C C WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C D VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C PC15 E BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL F BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 G CR MII_COL BB TA PB30 TDO TMS TRST H VFLS_1 RSV BURST BG PB28 TDI VDDL PA10 MDIO J ALE_A DSCK VFLS_0 FRZ GND TCK PB25 PB24 K KR AS BADDR30 HRESET PC5 PC7 PA8 PA9 L OP0 OP1 OP2 RSTCONF VDDH PD13 PA2 PC6 PA3 M OP3BADDR29 BADDR28 VDDL EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14 D9 IRQ1 PD3 N/C PC4 PA1 PB15 N PD8 PD15 VDDL PA0 P XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 R PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 T VDDL IP_A7 N/C 2 IP_A0 3 IP_A2 IP_A4 4 DP3 DP2 5 D31 D30 6 D28 D7 7 D6 D22 8 D19 VDDL 9 D5 D18 10 D2 D3 11 D27 D1 12 D13 D4 13 D0 PD5 PD10 N/C U D8 MII_TXEN PD7 14 15 16 N/C 17 Figure 63. Pinout of the PBGA Package - non-JEDEC MPC852T Hardware Specifications, Rev. 3.1 68 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 31. Pin Assignments - non-JEDEC Name A[0:31] Pin Number Type C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10, Three-state (3.3 V only) D9, C12, B9, C11, C10, E9 F9 Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Output TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31] F8 C2 H4 E2 F3 G5 F4 E3 H3 Bidirectional Active Pull-up (3.3 V only) Bidirectional Active Pull-up (3.3 V only) Open-drain Bidirectional Active Pull-up (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) K2 G2 Input (3.3 V only) T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13, T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9, T12, T7, R7, U6, T6 R5 Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6 R6 U5 T5 MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 69 Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name BR BG BB FRZ IRQ6 IRQ0 IRQ1 IRQ7 M_TX_CLK CS[0:5] CS6 CS7 WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2-3] UPWAITA GPL_A4 GPL_A5 PORESET F2 H5 G4 J5 Pin Number Type Bidirectional (3.3 V only) Bidirectional (3.3 V only) Bidirectional Active Pull-up (3.3 V only) Bidirectional (3.3 V only) R14 N12 P13 Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) C3, B3, E4, D4, F7, D5 E5 B4 E7 Output Output Output Output D7 Output B6 Output C6 Output B7, E8, D8, C8 D6 Output Output E6 Output B5, C5 Output D3 Bidirectional (3.3 V only) F5 R2 Output Input (3.3 V only) MPC852T Hardware Specifications, Rev. 3.1 70 Freescale Semiconductor Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG L5 K5 N4 P2 N2 P7 P3 J2 F6 C4 P4 U3 N7 T4 Pin Number Type Input (3.3 V only) Open-drain Open-drain Analog Output Analog Input (3.3 V only) Output Input (3.3 V only) Output Output Output Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) N6 U4 P6 N8 T3 J3 J4, H2 Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) L2 L3 L4 Bidirectional (3.3 V only) Output Bidirectional (3.3 V only) M2 Bidirectional (3.3 V only) M4, M3 K4 Output Output MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name AS PA11 RXD3 PA10 TXD3 PA9 RXD4 PA8 TXD4 PA3 CLK5 BRGO3 TIN3 PA2 CLK6 TOUT3 PA1 CLK7 BRGO4 TIN4 PA0 CLK8 TOUT4 PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 K3 F17 Pin Number Type Input (3.3 V only) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (5 V-tolerant) J16 K17 K16 L17 L15 Bidirectional (5 V-tolerant) M16 Bidirectional (5 V-tolerant) N17 Bidirectional (5 V-tolerant) F14 Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) G14 E16 H14 MPC852T Hardware Specifications, Rev. 3.1 72 Freescale Semiconductor Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name PB25 SMTXD1 PB24 SMRXD1 PB15 BRGO3 PC15 DREQ0 PC13 RTS3 PC12 RTS4 PC7 CTS3 PC6 CD3 PC5 CTS4 SDACK1 PC4 CD4 PD15 MII_RXD3 PD14 MII_RXD2 PD13 MII_RXD1 PD12 MII_MDC PD11 RXD3 MII_TX_ER PD10 TXD3 MII_RXD0 J15 Pin Number Type Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) J17 M17 D17 F15 F16 K15 L16 K14 M15 Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) N15 P17 L14 P16 R17 T16 Bidirectional (5 V-tolerant) MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 73 Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name PD9 RXD4 MII_TXD0 PD8 TXD4 MII_RX_CLK PD7 RTS3 MII_RX_ER PD6 RTS4 MII_RX_DV PD5 MII_TXD3 PD4 MII_TXD2 PD3 MII_TXD1 TMS P15 Pin Number Bidirectional (5 V-tolerant) Type N14 Bidirectional (5 V-tolerant) U16 Bidirectional (5 V-tolerant) P14 Bidirectional (5 V-tolerant) T15 Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Output (5 V-tolerant) Input Bidirectional (5 V-tolerant) Output (5 V-tolerant) Input PLL analog GND PLL analog GND PLL analog VDD R15 N13 G16 TDI DSDI TCK DSCK TRST H15 J14 G17 TDO DSDO MII_CRS MII_MDIO G15 C7 H17 MII_TX_EN U15 MII_COL VSSSYN VSSSYN1 VDDSYN G3 P5 R4 R3 MPC852T Hardware Specifications, Rev. 3.1 74 Freescale Semiconductor Mechanical Data and Ordering Information Table 31. Pin Assignments - non-JEDEC (continued) Name GND VDDL VDDH N/C Pin Number H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9, K10, K11, K12, L7, L8, L9, L10, L11, L12 B8, D2, E17, H16, M5, N3, T2, N16, U9 G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 Power Power Power Type No-connect MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 75 Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note (order number: AN1231/D) that is available from your local Motorola sales office. Figure 64 shows the mechanical dimensions of the PBGA package. MPC852T Hardware Specifications, Rev. 3.1 76 Freescale Semiconductor Mechanical Data and Ordering Information NOTES: 1. All dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M--1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX. Figure 64. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 77 Document Revision History 17 Document Revision History Table 32 lists significant changes between revisions of this document. Table 32. Document Revision History Revision 3.1 3.0 Date 1/18/2005 11/2004 Document template update. * Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values * Added a footnote to Spec 41 specifying that EDM = 1 * Broke the Section 16.1, "Pin Assignments," into 2 smaller sections for the JEDEC and non-JEDEC pinouts. Put 852T on the 1st page in place of 8245. Figure 62 on page 59 had overbars added on signals CR (pin G2) and WAIT_A (pin P4). Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and B29d to show that TRLX can be 0 or 1. Changed the SPI Master Timing Specs. 162 and 164 Changed the package drawing in Figure 15-63 Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note: solder sphere composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63 Changed Table 15-30 Pin Assignments for the PLL Pins VSSSYN1, VSSSYN, VDDSYN Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges. In Table 15-30, specified EXTCLK as 3.3 V. Added fast Ethernet controller to the features Added values for 80 and 100 MHz Initial release Changes 2.0 12/2003 1.8 7/2003 1.7 1.6 1.5 5/2003 4/2003 4/2003 1.4 1.3 1.2 1.1 1 0 2/2003 1/2003 1/2003 12/2002 11/2002 10/2002 MPC852T Hardware Specifications, Rev. 3.1 78 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor 79 How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-0047 Japan 0120 191014 +81 3 3440 3569 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@ hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. MPC852TEC Rev. 3.1 01/2005 |
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